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? semiconductor components industries, llc, 2005 november, 2005 ? rev. 2 1 publication order number: DAP011/d customer specific device from on semiconductor pwm current?mode controller for high?power universal off?line supplies housed in an so?14 package, the DAP011/DAP011c represents an enhanced version of the maximus, dap008, controller. due to its high drive capability, speedking drives large gate?char ge mosfets which, together with internal ramp compensation and a user selectable frequency jittering, ease the design of modern ac/dc adapters. with an internal structure operating at a fixed 65/100 khz frequency, the controller directly connects to the high?voltage rail for a loss less and clean startup sequence. current?mode control also provides an excellent input audio?susceptibility and inherent pulse?by?pulse control. internal ramp compensation easily prevents subharmonic oscillations from taking place in continuous conduction mode designs. when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the so?called skip cycle mode and provides excellent efficiency at light loads. because this occurs at a user adjustable low peak current, no acoustic noise takes place. due to a proprietary softskip technique, the absence of sharp transitions during skip mode significantly reduces acoustical noise. the DAP011/DAP011c features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses while the device enters a safe burst mode, trying to restart. once the default has gone, the device auto?recovers. by implementing a timer to acknowledge a fault condition, independently from the auxiliary supply, the designer?s task is eased when stringent fault mode conditions need to be met. a dedicated input helps triggering a latch?off circuitry which permanently disables output pulses. features ? current?mode control with adjustable skip?cycle capability ? internal ramp compensation ? adjustable frequency jittering for better emi signature ? auto?recovery internal output short?circuit protection ? adjustable timer for improved short?circuit protection ? dedicated latch input ? +500 ma/?800 ma peak current capability ? fixed frequency versions at 65/100 khz ? 5.0 v ? 5.0 ma reference voltage ? internal temperature shutdown ? direct optocoupler connection ? extremely low no?load standby power ? adjustable soft?start ? this is a pb?free device* typical applications ? high power ac/dc converters for tvs, set?top boxes, etc. ? offline adapters for notebooks ? all power supplies device package shipping ? ordering information so?14 (pb?free) 2500 / tape & ree l marking diagram pin connections DAP011 DAP011c soic?14 d suffix case 751a (top view) 1 14 DAP011/DAP011c awlywwg 1 14 a = assembly location wl = wafer lot y = year ww = work week g = pb?free package ctimer latch nc jitter skip fb cs 1 2 3 4 5 6 7 14 13 12 11 10 9 8 hv nc nc ref vcc drv gnd ?for information on tape and reel specifications, including par t orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. (65 khz) (100 khz) fosc DAP011/DAP011c free datasheet http:///
DAP011/DAP011c http://onsemi.com 2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 DAP011/DAP011c *see note ovp freq. jitter skip adj. + hv?bulk 5 v ref. v out + gnd ramp gnd timer delay + *this resistor prevents from negatively biasing the hv pin (14) at power?off. typical value is 4.7 k . figure 1. typical application example 1 nc ? ? 2 latch input voltage to latch comparator by bringing this pin above 3.0 v, e.g. via a zener or an ntc, the circuit permanently latches?off. 3 ctimer timer/soft?start delay wiring a capacitor to ground helps selecting the timer duration. 10% of this duration fixes the soft?start period. 4 jitter frequency jittering speed this pin offers a way to adjust the frequency modulation pace. 5 skip skip cycle adjustment by connecting a resistor to ground, it becomes possible to alter the default skip cycle level. 6 fb feedback pin hooking an optocoupler collector to this pin will allow regulation. 7 cs current sense + ramp compensation this pin monitors the primary peak current but also offers a mean to introduce ramp compensation. 8 gnd ? the controller ground. 9 drv driver output the driver?s output to an external mosfet. 10 vcc supplies the controller this pin is connected to an external auxiliary voltage. 11 ref. reference voltage this pin delivers 5.0 v and sources up to 5.0 ma. 12 nc ? non?connected for improved creepage. 13 nc ? non?connected for improved creepage. 14 hv high?voltage input connected to the bulk capacitor, this pin powers the internal current source to deliver a startup current. free datasheet http:///
DAP011/DAP011c http://onsemi.com 3 1 2 latch + ? 20 s time constant s q q r + v latch 4 v reset + ? soft?start ended v cc and logic management 4 v reset power reset v ccon v cc(min) v cclatch + + ? ic1 hv 14 ipflag fault 13 12 11 ref . uvlo 10 v cc 9 drv v dd 65/100 khz clock s q q r + ? i clamp ss fault/startup skip ipflag ramp /3 skip 6 fb v dd rfb 7 cs leb 8 gn d + ? v skip 5 skip r skip i skip v dd + 2.icjit + ? icjit v dd frequency modulation + ? fault + v timss + v timfault skip, soft?start ipflag power on reset v dd i tim 4 jitter 3 timer figure 2. internal circuit architecture free datasheet http:///
DAP011/DAP011c http://onsemi.com 4 maximum ratings rating symbol value unit power supply voltage, v cc pin, continuous voltage v cc 20 v transient power supply voltage, duration < 10 ms, iv cc < 20 ma ? 25 v maximum voltage on low power pins (except pin 9, pin 10, pin 5 and pin 14) ? ?0.3 to 10 v maximum voltage on pin 5 ? 5.0 v thermal resistance, junction?to?air r ja 120 c/w thermal reference junction?to?lead (note 3) p si j l 40 c/w maximum junction temperature t jmax 150 c storage temperature range ? ?60 to +150 c esd capability, hbm model (all pins except hv) ? 2.0 kv esd capability, machine model ? 200 v maximum voltage on pin 14 (hv) ? ?0.3 to 500 v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil?std?883, method 3 015. machine model method 200 v 2. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 3. minimum pad fr4 board 1 oz copper. free datasheet http:///
DAP011/DAP011c http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?5 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted.) characteristic symbol pin min typ max unit supply section v cc increasing level at which the current source turns?off v ccon 10 11.8 12.8 13.8 v v cc level at which output pulses are stopped v cc(min) 10 8.0 9.0 10 v v cc decreasing level at which the latch?off phase ends v cclatch 10 ? 6.5 ? v internal latch reset level v ccreset 10 ? 5.0 ? v minimum voltage difference between v cclatch and v ccreset reset hyst ? 1.0 ? ? v internal ic consumption, no output load on pin 9 DAP011 DAP011c i cc1 10 ? ? 1.2 1.3 ? ? ma internal ic consumption, 1.0 nf output load on pin 9 DAP011 DAP011c i cc2 10 ? ? 1.9 2.5 ? ? ma internal ic consumption, latch?off phase i cc3 10 ? 0.6 ma reference voltage, i out = 1.0 ma, t j = 25 c v ref1 11 4.9 5.0 5.1 v reference voltage, i out = 5.0 ma v ref2 11 4.8 ? 5.13 v maximum output current capability i refout 11 5.0 ? ? ma decoupling capacitor connected to pin 11 c ref 11 100 ? ? nf internal startup current source (t j > ?5 c) ? high?voltage pin biased to 60 v dc. high?voltage current source, v cc = 10 v (note 4) i c2 14 2.0 4.0 ? ma high?voltage current source, v cc = 0 i c1 14 200 500 650 a v cc transition level for i c1 to i c2 toggling point v th 14 ? 1.8 ? v leakage current for the high voltage source, v pin 14 = 250 vdc i leak 14 ? 35 ? a drive output (lothar like) output voltage rise?time @ c l = 1.0 nf, 10?90% of a 12 v output signal t r 9 ? 40 ? ns output voltage fall?time @ c l = 1.0 nf, 10?90% of a 12 v output signal t f 9 ? 15 ? ns source resistance r oh 9 ? 12 ? sink resistance r ol 9 ? 7.0 ? current comparator input bias current @ 1.0 v input level on pin 7 i ib 7 ? 0.02 ? a maximum internal current setpoint ? t j = 25 c i limit1 7 0.95 1.0 1.05 v maximum internal current setpoint ? t j from ?5 to 125 c i limit2 7 0.93 1.0 1.07 v default internal voltage setpoint for skip cycle operation v lskip 7 ? 350 ? mv propagation delay from current detection to gate off state t del 7 ? 100 150 ns leading edge blanking duration t leb 7 ? 200 ? ns soft?start duration, c timer = 0.22 f tss ? ? 10 ? ms internal oscillator oscillation frequency DAP011 DAP011c f osc ? 60 92 65 100 70 108 khz maximum duty?cycle d max ? 76 80 84 % frequency jittering in percentage of f osc DAP011 DAP011c f jitter ? ? ? 5.0 6.0 ? ? % swing frequency with a 22 nf capacitor to pin 4 f swing 4 ? 300 ? hz jittering modulator charging current i cjit 4 ? 20 ? a jittering capacitor peak voltage v cjitp 4 ? 2.15 ? v jittering capacitor valley voltage v cjitv 4 ? 0.75 ? v 4. min. value for t j = 125 c (see figure 10). free datasheet http:///
DAP011/DAP011c http://onsemi.com 6 electrical characteristics (continued ) (for typical values t j = 25 c, for min/max values t j = ?5 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted.) characteristic symbol pin min typ max unit feedback section internal pullup resistor r up 6 ? 20 ? k pin 6 to current setpoint division ratio i ratio ? ? 3.0 ? ? skip cycle generation internal skip reference current i skip 5 ? 40 ? a pin 5 internal output impedance (note 5) z out 5 ? 25 ? k default skip mode level v skip 5 ? 1.0 ? v internal ramp compensation internal ramp level @ 25 c (note 6) v ramp 7 ? 1.8 ? v internal ramp resistance to cs pin r ramp 7 ? 20 ? k protections latching level input v latch 2 2.85 3.05 3.25 v delay before latch confirmation t latch?del ? ? 20 ? s timer level completion v timfault 3 ? 4.3 ? v timer capacitor charging current i tim 3 ? 10 ? a timer length, c timer = 0.22 f typical t imerl 3 ? 100 ? ms temperature shutdown t sd ? 140 ? ? c temperature shutdown hysteresis t sd_hys ? ? 40 ? c 5. maximum voltage on pin 5 is 5.0 v. 6. a 15 k resistor is connected from pin 7 to the ground for the measurement. free datasheet http:///
DAP011/DAP011c http://onsemi.com 7 12.6 12.7 12.8 12.9 13 ?25 0 25 50 75 100 125 temperature ( c) voltage (v) figure 3. v ccon voltage versus temperature 8.9 8.95 9 9.05 9.1 ?25 0 25 50 75 100 125 temperature ( c) voltage (v) figure 4. v ccmin voltage versus temperature 1 1.1 1.2 1.3 1.4 1.5 ?25 0 25 50 75 100 125 temperature ( c) current (ma) figure 5. current consumption i cc1 versus temperature (driver unloaded) 1.75 1.95 2.15 2.35 2.55 2.75 ?25 0 25 50 75 100 125 temperature ( c) current (ma) figure 6. current consumption i cc2 versus temperature (driver loaded with 1 nf) 0.3 0.33 0.36 0.39 0.42 ?25 0 25 50 75 100 125 temperature ( c) current (ma) figure 7. current consumption in latch?off phase versus temperature 4.8 4.9 5 5.1 5.2 ?25 0 25 50 75 100 125 temperature ( c) voltage (v) figure 8. 5 ma loaded reference voltage evolution versus temperature DAP011c DAP011 DAP011c DAP011 free datasheet http:///
DAP011/DAP011c http://onsemi.com 8 300 350 400 450 500 550 ?25 0 25 50 75 100 125 temperature ( c) figure 9. high voltage current source level evolution versus temperature when v cc = 0 v current ( a) 2.5 3 3.5 4 4.5 5 ?25 0 25 50 75 100 125 temperature ( c) figure 10. high voltage current source level evolution versus temperature when v cc = 10 v current (ma) 0 10 20 30 40 50 ?25 0 25 50 75 100 125 temperature ( c) figure 11. high voltage current source leakage versus temperature current ( a) 10 12 14 16 18 20 ?25 0 25 50 75 100 125 temperature ( c) figure 12. driver source output impedance evolution versus temperature impedance ( ) 5 7 9 11 13 15 ?25 0 25 50 75 100 125 impedance ( ) temperature ( c) figure 13. driver sink impedance evolution versus temperature 1.018 1.019 1.02 1.021 1.022 ?25 0 25 50 75 100 125 temperature ( c) figure 14. maximum peak current limit evolution with temperature voltage (v) free datasheet http:///
DAP011/DAP011c http://onsemi.com 9 temperature ( c) frequency (khz) figure 15. DAP011 oscillator frequency with temperature 62 63 64 65 66 ?25 0 25 50 75 100 125 1.72 1.74 1.76 1.78 1.8 1.82 ?25 0 25 50 75 100 125 temperature ( c) voltage (v) figure 16. DAP011c oscillator frequency with temperature 19 19.5 20 20.5 21 21.5 ?25 0 25 50 75 100 1 25 resistance (k ) temperature ( c) figure 17. ramp compensation voltage evolution with temperature 3.02 3.03 3.04 3.05 3.06 3.07 ?25 0 25 50 75 100 125 temperature ( c) figure 18. ramp compensation resistor value evolution with temperature voltage (v) figure 19. latch level evolution with temperature temperature ( c) frequency (khz) 95 97 99 101 105 ?25 0 25 50 75 100 12 5 103 free datasheet http:///
DAP011/DAP011c http://onsemi.com 10 application information introduction speedking implements a standard current mode architecture where the switch?off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part?count is the key parameter, particularly in low?cost ac/dc adapters, open?frame power supplies etc. due to its high voltage technology, the DAP011/DAP011c incorporates all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as an adjustable emi jittering and a fault timer. ? current?mode operation with internal ramp compensation: implementing peak current mode control, the DAP011/DAP011c offers an internal ramp compensation signal that can easily by summed up to the sensed current. subharmonic oscillations can thus be fought via the inclusion of a simple resistor. ? internal high?voltage startup switch: reaching a low no?load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. thanks to an internal logic, the controller disables the high?voltage current source after startup which no longer hampers the consumption in no?load situations. ? emi jittering: a dedicated pin offers the ability to vary the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. ? skip?cycle capability: a continuous flow of pulses in not compatible with no?load standby power requirements. slicing the switching pattern in bunch of pulses drastically reduces overall losses but can, in certain cases, bring acoustic noise in the transformer. thanks to a skip operation taking place at low peak currents only, no mechanical noise appears in the transformer. also, activating the soft?start during skip cycle brings so?called softskip benefits, greatly reducing acoustical noise in the transformer. ? internal soft?start: a soft?start precludes the main power switch from being stressed upon startup. its duration is equal to 10% of the fault timer, e.g. 10ms for a 100 ms timer duration. ? latch input: by monitoring pin 2, the controller detects when it is brought above a latching level via a zener (ovp) or a ntc (otp), or both. when the latch is detected, all pulses are permanently disabled and v cc goes up and down, maintaining the latch condition. when the user cycles v cc below 5.0 v, the controller gets reset and attempts to restart. ? short?circuit protection: short?circuit and especially over?load protection are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the auxiliary winding level does not properly collapse in presence of an output short). here, every time the internal 1.0 v maximum peak current limit is activated, an error flag, i p flag, is asserted and a time period starts, thanks to an adjustable timer. if the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into a latch?off phase, operating in a low?frequency burst?mode. to limit the fault output power, a divide?by?two circuitry is installed on the v cc pin and requires twice a startup sequence before another attempt to restart is. as soon as the fault disappears, the smps resumes operation. the latch?off phase can also be initiated, more classically, when v cc drops below v cc(min) (9.0 v typical). free datasheet http:///
DAP011/DAP011c http://onsemi.com 11 startup sequence when the power supply is first connected to the mains outlet, the internal current source is biased and charges up the v cc capacitor. when the voltage on this v cc capacitor reaches the v ccon level (typically 12.8 v), the current source turns off, reducing the amount of power being dissipated. at this time, the v cc capacitor only supplies the controller, and the auxiliary supply should take over before v cc collapses below v cc(min) . figure 20 shows the internal arrangement of this structure: figure 20. the current source brings v cc above 15 v and then turns off ? + + ic1 or 0 v cc on v cc latch hv 14 10 8 in some fault situations, a short?circuit can purposely occur between v cc and gnd. in high line conditions (vhv = 370 vdc) the current delivered by the startup device will seriously increase the junction temperature. for instance, since ic1 equals 2 ma (the minimum corresponds to the highest t j ), the device would dissipate 370 x 2 m = 740 mw. to avoid this situation, the controller includes a novel circuitry made of two startup levels, ic1 and ic2. at power?up, as long as v cc is below a certain level (1.8 v typical), the source delivers ic1 (around 500 a typical), then, when v cc reaches 1.8 v, the source smoothly transitions to ic2 and delivers its nominal value. as a result, in case of short?circuit between v cc and gnd, the power dissipation will drop to 370 x 500 = 185 mw. figure 21 portrays this particular behavior: figure 21. the startup source now features a dual level startup current v cc v cc on vth cv cc = 22 f ic2 min ic1 min t1 t2 the first startup period is calculated by the formula c x v = i x t, which implies a 22 x 1.5 / 350 = 94ms startup time for the first sequence. the second sequence is obtained by changing to 2 ma with a v of v ccon ? v ccth = 12.8 ? 1.5 = 11.3 v, which finally leads to a second startup time of 12.8 x 22 / 2 m = 140 ms. the total startup time becomes 94 m + 140 m = 235 ms. please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. free datasheet http:///
DAP011/DAP011c http://onsemi.com 12 as soon as v cc reaches v ccon , drive pulses are delivered on pin 9 and the auxiliary winding increases the voltage on the v cc pin. because the output voltage is below the target (the smps is starting up), the controller smoothly ramps?up the peak current to i max (1.0 v / r sense ) which is reached after a typical soft?start period. this soft?start period lasts typically 10% of what has been selected for the fault timer via pin 3. as soon as the peak current setpoint reaches its maximum (during the startup period but also anytime an overload occurs), an internal error flag is asserted, i p flag, indicating that the system has reached its maximum current limit set point (i p = i p maximum). as soon as the error flag gets asserted, the current source on pin 3 is activated and charges up the capacitor connected to this pin. if the error flag is still asserted when the timer capacitor has reached the threshold level v tim fault, (which is about 100 ms with a 0.22 f typically), then the controller assumes that the power supply has really undergone a fault condition and immediately stops all pulses to enter a safe burst operation. figure 22 depicts the v cc evolution during a proper startup sequence, showing the state of the error flag: figure 22. an error flag gets asserted as soon as the current setpoint reaches its upper limit (1.0 v/r sense ) here the timer lasts 100 ms, a 0.22 f capacitor being connected to pin 3 free datasheet http:///
DAP011/DAP011c http://onsemi.com 13 short?circuit or overload mode there can be various events that force a fault on the primary side controller. we can split them in different situation, each having a particular configuration: 1. the converter regulates but the auxiliary winding collapses: this is a typical situation linked to the usage of a constant?current / constant?voltage (cc?cv) type of controller. if the output current increases, the voltage feedback loop gives up and the current loop takes over. it means that v out goes low but the feedback loop is still closed because of the output current monitoring. therefore, seen from the primary side, there is no fault. however, there are numerous charger applications where the output voltage shall not go below a certain limit, even if the current is controlled. to cope with this situation, the controller features a precise undervoltage lockout comparator biased to a v cc(min) level. when this level is crossed, whatever the other pin conditions, pulses are stopped and the controller enters the safe hiccup mode, trying to restart. figure 23 shows how the converter will behave in this situation. if the fault goes away, the smps resumes operation. figure 23. first fault mode case, the auxiliary winding collapses but feedback is still there free datasheet http:///
DAP011/DAP011c http://onsemi.com 14 2. in the second case, the converter operates in regulation, but the output is severely overloaded. however, due to the bad coupling between the power and the auxiliary windings, the controller v cc does not go low. the peak current is pushed to the maximum and the timer starts to count. upon completion, all pulses are stopped and dual startup hiccup mode is entered. if the fault goes away, the smps resumes operation. figure 24. this case is similar to a short?circuit where v aux does not collapse free datasheet http:///
DAP011/DAP011c http://onsemi.com 15 3. a second case exists where the short?circuit makes the auxiliary level go below v cc(min) . in that case, the timer length is truncated and all pulses are stopped. the double hiccup fault mode is entered and the smps tries to restart. when the fault is removed, the smps resumes operation. figure 25. this case is similar to a short?circuit where v aux does collapse free datasheet http:///
DAP011/DAP011c http://onsemi.com 16 the recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the v cc capacitor. figure 26 details the various time portion a hiccup is made of: drv 100 ms 100 ms t1 t2 t3 t?1 t?2 latch?off phase level logic reset level uvlo low v cc uvlo high figure 26. the burst period is ensured by the v cc capacitor charge/discharge cycle if by design we have selected a 22 f v cc capacitor, it becomes easy to evaluate the burst period and its duty?cycle. this can be done by properly identifying all time events on figure 26 and applying the classical formula: t v c i (eq. 1) ? t1: i = i cc3 = 600 a, v = 9 ? 6.5 = 2.5 v t1 = 91 ms ? t2: i = 3 ma, v = 12.8 ? 6.5 = 6.3 t1 = 46 ms ? t3: i = 600 a, v= 12.8 ? 6.5 = 6.3 v t1 = 231ms ? t?1 = t1 = 91 ms ? t?2 = t2 = 46 ms the total period duration is thus the sum of all these events which leads to t fault = 505 ms. if t pulse = 100 ms, then our burst duty?cycle equals 100/(505+100) 16.5%, which is good. should the user like to further decrease or, to the contrary, increase this duty?cycle, changing the v cc capacitor is an easy job. latch?off and overvoltage protection speedking features a fast comparator that permanently monitors pin 2 level. figure 27 details how it is internally arranged: figure 27. a comparator monitors pin 2 and latches off the part in case the threshold is reached ? + r upper r lower v latch + + 20 s time constant v cc aux aux 5 v reset r s q q latched fault c1 10 nf 2 free datasheet http:///
DAP011/DAP011c http://onsemi.com 17 figure 28. the part is reset when v cc reaches 5.0 v if for any reason pin 2 level grows above 3.0 v, the part immediately stops pulsing and stays latched in this position until the user cycles down the power supply. the reset actually occurs if v cc drops below 5.0 v. figure 28 details the operating diagrams in case of a fault. please note the presence of rc time constant on the comparator output, aimed to filtering any spurious oscillations linked to an eventual noise presence. the typical value of this time constant is 20 s. internal reference voltage a 5.0 v reference voltage is pinned out on pin 11 and can source up to 5.0 ma. figure 29 details how the reference voltage can be externally used, for instance to build a precise over temperature protection (otp) circuitry. this 5.0 v source is shut down during the startup phase and goes low as soon as v cc crosses v cc(min) . it stays low during the double hiccup mode to keep the consumption to the lowest. we recommend to wire a 100 nf from this pin to ground in order to improve the noise immunity. figure 29. the reference voltage is used with the latchoff input to trigger the circuit in presence of an otp ? + t r lower v latch + 20 s time constant 5 v reset r s q q latched fault c1 10 nf 2 v ref + 11 uvlo fault free datasheet http:///
DAP011/DAP011c http://onsemi.com 18 soft?start and fault timer the speedking features an internal soft?start circuit activated during the power on sequence (pon) but also during skip cycle to reduce the acoustical noise (see skip cycle section). as soon as v cc reaches v ccon , the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 1.0 v / r sense ). the peak current is clamped at 1.0 v / r sense through the entire soft?start period until the supply enters regulation. figure 30 shows a typical startup shot. v ccon 12 v 6.9v figure 30. soft?start is activated during a startup sequence an ocp condition (or during skip?cycle ? 500 s skip ramp) 10% of timer or 500 s at skip mode figure 31. soft?start is activated during a startup sequence, an ocp condition (or during skip?cycle ? 500 s skip ramp) + ? + ? + + v timss v timfault i tim v dd timer fault soft?start ended skip, soft?start power on reset ipflag 3 free datasheet http:///
DAP011/DAP011c http://onsemi.com 19 to simplify the circuit architecture, the timer pin also shares the soft?start comparator, as figure 31 details. that means that the soft?start is linked to the timer duration by a ratio of 0.1 or 10% roughly. if we select a 100 ms timer period, then the soft?start duration will be 10 ms. figure 32 details pin 3 voltages during a soft?start sequence or a skip?cycle activity. the soft?start capacitor is reset by either the soft?start completion within the burst or by the skip comparator (500 s soft skip ramp) if the burst length is shorter than the soft?start duration. figure 32. soft?start is also activated during skip cycle to offer a smooth current ramping wave shape how to calculate the timer capacitor value? by simply apply v x c = i x t relationship. if we look at figure 31, we can see that the timer is completed when v pin3 reaches 4.0 v. if we have a 20 a charging current and we want 90 ms of timer duration, then c is obtained by: c = i x t / v = 20 x 100m / 4 = 500 nf. if we select a 0.47 f, we end?up with a final duration of 94 ms. the soft?start being 10% of this value, we will see a soft?start sequence of 9.4 ms. internal ramp compensation ramp compensation is a known mean to cure subharmonic oscillations. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty?cycle greater than 50%. to lower the current loop gain, one usually injects between 50 and 100% of the inductor downslope. figure 33 depicts how internally the ramp is generated. please note that the ramp signal will be disconnected from the cs pin, during the off time. free datasheet http:///
DAP011/DAP011c http://onsemi.com 20 figure 33. inserting a resistor in series with the current sense information brings ramp compensation and stabilizes the converter in ccm operation + ? cs leb 20k rcomp rsense from fb setpoint 2v 0v on latch reset in the speedking, the oscillator ramp features a 2.0 v swing. if our clock operates at a 65 khz pace, then the oscillator slope corresponds to a 130 mv/ s ramp. in our flyback design, let?s assume that our primary inductance l p is 350 h, and the smps delivers 12 v with a n p :n s ratio of 1:0.1. the off time primary current slope is thus given by: (v out v f ) n s n p l p 371 ma sor37mv s (eq. 2) when projected over an r sense of 0.1 , for instance. if we select 75% of the downslope as the required amount of ramp compensation, then we shall inject 27 mv/ s. our internal compensation being of 130 mv, the divider ratio (divratio) between r comp and the 20 k is 0.207. a few lines of algebra to determine r comp : 20 k divratio (1 divratio) 5.2 k (eq. 3) frequency jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. speedking offers a 5% ( 6% for DAP011c) deviation of the nominal switching frequency. the sweep sawtooth is internally generated and modulates the clock up and down with an adjustable period. figure 34 displays the internal arrangement around pin 4. it is actually a i ? 2i generator, producing a clean 50% duty?cycle sawtooth. if we take a 1.4 v swing on the jitter capacitor, then we calculate the needed value for a 3 ms period, or a 330 hz modulation speed, again applying the v x c = i x t relationship. we need 1.5 ms to ramp?up and 1.5 ms to ramp down, therefore: c = 20u x 1.5m / 1.4 = 21 nf. if we select a 22 nf, then our modulation frequency will be around 325 hz. figure 35 shows the relationship between the jitter ramp and the frequency deviation. figure 34. an internal ramp is used to introduce frequency jittering on the oscillator sawtooth ? + + icjit v dd ctimer frequency modulation 4 2.icjit jitter vcjitp vcjitv to clock circuit figure 35. modulation effects on the clock signal by the jittering sawtooth 65khz 68.9 khz 61.1 khz jitter ramp internal sawtooth adjustable skipping cycle mode speedking automatically skips switching cycles when the output power demand drops below a given level. this is accomplished by monitoring the fb pin. in normal operation, pin 5 imposes a peak current accordingly to the load value. if the load demand decreases, the internal loop asks for less peak current. when this setpoint reaches a fixed determined level, the ic prevents the current from decreasing further down and starts to blank the output pulses. the ic enters the so?called skip cycle mode, also named controlled burst operation. the default skip cycle current is internally frozen to 30% of the maximum peak current which is 350 mv/r sense the power transfer now depends upon the width of the pulse bunches (figure 38). suppose we have the following component values: primary inductance (l p ) = 350 h switching frequency (f sw ) = 65 khz i p skip = 600 ma (or 350 mv / r sense ) the theoretical power transfer is therefore: free datasheet http:///
DAP011/DAP011c http://onsemi.com 21 1 2 l p i p 2 f sw 4w (eq. 4) if this ic enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 4 . 0.1 = 400 mw. to better understand how this skip cycle mode takes place, a look at the operation mode versus the fb level immediately gives the necessary insight: 5.0 v, fb pin open 3.0 v upper dynamic range normal current mode operation 1.0 v skip?cycle operation i p min = 350 mv/r sense fb pin voltage figure 36. when fb is above the skip cycle threshold (1.0 v by default), the peak current cannot exceed 1.0 v / r sense . when the ic enters the skip cycle mode, the peak current cannot go below 1.0 v / 3 or around 350 mv / r sense . figure 38 shows different values of pulse widths when the smps starts?to?skip cycles at different power levels: figure 37. output pulses at various power levels (x = 5 s/div) p1 < p2 < p3 power p1 power p2 power p3 free datasheet http:///
DAP011/DAP011c http://onsemi.com 22 315.4u 882.7u 1.450m 2.017m 2.585m 300.0m 200.0m 100.0m 0 25% of max ip max peak current the skip?cycle takes place at low peak currents which guaranties noise free operation figure 38. figure 39. a smooth ramping current in skip?cycle as we have stated several times, the peak current in skip?cycle will not immediately ramp?up to its default value. to limit the discontinuities in the transformer mechanical structure, and thus reduce the acoustic noise, the 500 s soft?skip ramp will be activated in skip cycle. figure 39 shows a typical shot, showing the peak current ramp?up. since pin 5 features an internal voltage source whose output impedance is 25 k , it is possible to alter the default skip value. a simple arrangement consists in connecting a resistor to ground in order to lower the setpoint. on the other hand, the setpoint can be increased, if necessary, by wiring a resistor to the reference voltage. figure 40 portrays these options. since pin 5 internal impedance is 25 k , it is simple to calculate the value of the resistor to decrease the v skip level (1.0 v typically). suppose we want to decrease it down to 800 mv. then, the resistor to connect to pin 5 is 0.8 / 40 = 20 k . to obtain a 20 k from an original 25 k value, we need to parallel a (20 k x 25 k) / (25 k?20 k) = 100 k . free datasheet http:///
DAP011/DAP011c http://onsemi.com 23 figure 40. due to pin 4, it is easy to alter the default skip level ? + + iskip v dd to decrease vskip peak setpoint latch reset 6 vskip 5 skip rskip v dd rfb to increase vskip 11 vref vref fb uvlo fault /3 free datasheet http:///
DAP011/DAP011c http://onsemi.com 24 package dimensions soic?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 DAP011/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative. free datasheet http:///

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